EIT system design using FPGAs
Figure 1 shows the structure of the KHU Mark2.5 EIT system. It includes a DSP-based main controller, which is responsible for data communication with a PC through an isolated USB connection. There are multiple impedance measurement modules (IMMs) and each module includes a current source and a voltmeter. The intra-network controller arbitrates data exchanges among the main controller, IMMs, and external devices. We classified and implemented all functions of the system in two kinds of FPGAs; the intra-network controller FPGA and IMM FPGA.
Intra-network controller FPGA
Figure 2 shows the functional block diagram of the intra-network controller FPGA. We can configure the EIT system with different numbers of IMMs and one intra-network controller FPGA can accommodate up to 32 IMMs. By adding one intra-network controller FPGA, the maximum number of IMMs is increased by 32.
The FPGA handles the command and data exchanges between the main controller and the connected IMMs. In designing the FPGA, we considered the data throughput to the main controller and the connected IMMs. Since the connection to the main controller requires fast exchanges of a large amount of data from all IMMs, we interfaced the FPGA to the main controller DSP in its external memory space.
In the KHU Mark2.5 EIT system, each IMM is independent and all of them operate in parallel. We, therefore, adopted the star network topology with a dedicated FIFO-based synchronous serial communication channel to each IMM, which is denoted as TxRxD. To implement the pipelined operation for a maximum frame rate of 100 frames/sec [18], we used the double-buffered memory structure in each serial communication channel to transmit previous data and store new data simultaneously.
Decoding the commands from the main controller, the intra-network controller FPGA may transmit its own commands to the IMMs through the serial communication channels and setup them for a chosen data collection protocol. When it gets a trigger command from the main controller, it initiates a series of data acquisitions by distributing timing synchronization signals called SyncOut to all connected IMMs. Though all IMMs are independent and operate in parallel, their data acquisitions are synchronized by sharing the common clock and timing signals from the FPGA. After triggering the IMMs for their data acquisitions, the intra-network controller FPGA receives the measured data from the IMMs through the serial communications channels.
In certain applications, it is highly desirable to synchronize EIT data acquisitions and image reconstructions with physiological events such as respiration and cardiac function. For example, ECG-gated EIT imaging may separate relatively small conductivity changes related with cardiac function from larger changes associated with lung ventilation [21]. In the external event trigger mode, the intra-network controller FPGA gets a sequence of external trigger signals to control the subsequent EIT data acquisitions. Each event trigger signal may initiate one or multiple data acquisitions by distributing the synchronization signals SyncOut to the connected IMMs.
Regardless of the operating mode, the intra-network controller FPGA can send the EIT measurement timing signal to external devices. The signal provides accurate timing information of EIT data acquisitions, which can be used to synchronize the external device with the EIT system. It may also be used to analyze measured data of the external device together with EIT images in a synchronized way. We implemented all the connections to external devices using the digital signal isolator (ADuM3100, Analog Devices, USA) with the low-voltage differential signaling (LVDS) technique for electrical safety and noise suppression.
Impedance measurement module FPGA
Figure 3 shows the block diagram of the IMM FPGA. It receives the synchronization signal SyncOut from the intra-network controller and exchanges commands and data via the dedicated serial communication channel TxRxD. Each IMM FPGA operates independently for current injection and voltage measurement regardless of the behavior of other IMMs [18].
We define a projection as one current injection and simultaneous multiple voltage measurements. At least two IMMs are involved in the current injection since we need at least one current source and at least one current sink to form a balanced current source. Usually, all IMMs are used to measure the induced voltages. A scan is a collection of projections to produce a set of measured data for one image reconstruction.
Real-time EIT data acquisitions include a series of scans with multiple projections in each scan. Therefore, we constantly change parameters of current injections such as electrodes, frequencies, and amplitudes. Accordingly, there occur transients in the induced voltage signals. To properly handle all of these switchings and transients in the digitized voltage signals as well as analog signals, the IMM FPGA must carefully implements all critical timing and functional controls of the real-time EIT data acquisition process.
Timing controller
Before starting any data acquisition, the intra-network controller provides a chosen data collection protocol as a protocol table to each IMM. The timing controller decodes the table and stores the commands and data in its memory space for the required projections and scans. These include the parameters for waveform generation, current source calibration, data acquisition, preprocessing, and switch control.
After receiving the synchronization signal SyncOut from the intra-network controller, the timing controller initiates a series of current injections and synchronous voltage data acquisitions. It generates various timing signals to coordinate all the operations of the IMM. Carefully adjusted timing controls are required to properly implement the pipeline operations [18] and the intermittent transient removals. For each projection, it gets the demodulated voltage data and transmits them to the intra-network controller through the serial communication channel TxRxD.
Waveform generator
We chose the memory-based waveform generation method using the register-transfer level (RTL) FPGA design. We used two internal ROMs to separately store 1,000 16-bit data of the single-frequency and mixed-frequency sinusoidal waveforms. The frequency is controlled by using two variables of gapdata and clkcount as
(1)
(2)
where gapdata determines the incremental step size of the ROM address, t
u
p
d
a
t
e
is the address update time, and S
c
l
k
is the period of the system clock. We can choose frequencies in the range of 10 Hz to 500 kHz.
For each projection, the timing controller sends the waveform parameters including the chosen frequencies and amplitudes. The waveform generator reads the waveform data from the memory using the timing signals properly adjusted for the chosen sinusoidal frequency and sends the data to the external 16-bit DAC (AD9783, Analog Devices, USA). It also sets the registers of the DAC for its control.
The waveform generator sends a pulse called Phase0 to the voltage demodulator. The pulse indicates the beginning of each sinusoidal period for the phase-sensitive demodulation of the induced voltage signal.
Current source calibrator
The output voltage of the DAC is converted to current using a trans-conductance amplifier, whose output impedance was calibrated beforehand to at least 1 M Ω in the entire frequency range [18]. To achieve the calibrated output impedance, we should properly set the digital potentiometers (DS1267E-010, -050, Maxim Integrated Products, Inc., USA) in the trans-conductance amplifier and also in the generalized impedance converter (GIC) at the output of the amplifier. Getting the values of the digital potentiometers extracted from the calibration table for the chosen frequencies, the current source calibrator sets up the digital potentiometers before current injection in each projection. It also sets the multiplying DAC (AD9783, Analog Devices, USA) to adjust the amplitude of the sinusoidal voltage waveform to reduce the dc offset current within ±33 nA.
During the system calibration beforehand, the current source calibrator iteratively adjusts the digital potentiometers to find their values to achieve at least 1 M Ω output impedance. As described by Wi et al
[18], this should be done with the voltmeter calibration as well. During real-time operations, the current source calibrator keeps the calibration table in its memory space. The voltmeter calibrations to compensate phase and gain errors are not included in the IMM but in the system software of the PC.
Data acquisition controller
The data acquisition controller provides the control signals to the external 12-bit ADC (AD9235, Analog Devices, USA). To continuously read ADC data, it uses the double buffered structure with two internal RAMs for real-time pipelined data acquisitions. When one of the RAMs is full with a predetermined amount of data, it is connected to the phase-sensitive demodulator and the other RAM is used to store the next set of data. The 12-bit ADC data is sign-extended to the 18-bit representation and the data acquisition controller performs chosen real-time preprocessing functions such as overflow detection, noise peak removal, and averaging of maximum 64 sinusoidal periods of data.
Phase-sensitive demodulator
The phase-sensitive demodulator computes the in-phase (real-part) and quadrature (imaginary-part) components, V
r
and V
q
, respectively, of the induced voltage V
i
n
as
(3)
(4)
During the phase-sensitive demodulation, the 18-bit sign-extended ADC data are multiplied with the 16-bit sinusoidal data stored in the ROM of the waveform generator. To perform 1,000 34-bit additions, we used the 44-bit arithmetic architecture to prevent overflow. It is important to carefully allocate enough memory space to prevent data loss during fast real-time demodulations.
When we measure the induced voltage at multiple frequencies, the phase-sensitive demodulations are simultaneously performed for maximum three different frequencies. For more than three frequencies, the demodulations are repeated using the same acquired ADC data and the stored sinusoidal waveform data at those frequencies.
Functional and timing simulations of FPGAs
We used the software package Quartus II (Altera, USA) for the FPGA design and simulation. For the chosen FPGA (EP3C10F256, Altera, USA) at 45 MHz clock speed, we verified the design for its functions and timing. We assumed that the operating frequency of the EIT data acquisition was 11.25 kHz. We also assumed that current was injected between one neighboring electrode pair and induced voltages were measured between all neighboring electrode pairs. After finishing the simulation of each part separately, we simulated the complete FPGA design including both the intra-network controller FPGA and IMM FPGAs.
Phantom experiments of fast multi-frequency imaging
Multi-frequency imaging requires fast data acquisitions at chosen operating frequencies. In the multi-frequency waveform multiplexing method [4], currents are injected in a waveform of mixed sinusoids with multiple frequencies. Figure 4 shows an example of injecting current with three different frequencies. Each voltmeter simultaneously demodulates the induced voltages at those three frequencies at the same time. We used three frequencies considering the safe levels of injection currents and SNRs of induced voltages at chosen frequencies [22].
Animal experiments of ECG-gated imaging
We performed in vivo animal experiments using a beagle (9 years old, female, 13 kg). The experimental protocol was approved by the Institutional Animal Care and Use Committee at Kyung Hee University. Putting the animal under anesthesia following the process described in Oh et al
[23], we shaved the hair around the chest and attached the EIT electrode belt with 16 Ag/AgCl electrodes. We also attached a separate respiration monitoring belt and ECG electrodes as shown in Figure 5. The experimental protocol was approved by the Institutional Animal Care and Use Committee at Kyung Hee University (KHUASP(SU)-11-07).
We used a custom designed device to acquire ECG and respiration signals at 500 Hz sampling frequency. Detecting R waves of the acquired ECG signal, we triggered a series of EIT scans at each R wave. We also triggered a series of EIT scans at a predetermined phase of each respiration cycle.